By Topic

Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Masaru Izawa ; Nano-process Res. Dept., Hitachi, Ltd., Kokubunji ; Masaru Kurihara ; Junichi Tanaka ; Kenji Kawai
more authors

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process.

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:22 ,  Issue: 2 )