A single-chip CMOS bluetooth v. 2.1 radio SoC

Bluetooth
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radios are becoming pervasive in small, battery-powered devices. This is being driven by the reduced area requirements, cost, and power consumption of Bluetooth chips. As process technology scales down to 0.13 mum CMOS and beyond, the opportunities to trade off digital complexity to reduce analog requirements can enable optimized radio designs. This article presents an architecture on both the transmitter and receiver that can optimize this digital/analog trade-off while still meeting all system requirements. A polar transmitter is presented that is capable of transmitting both basic rate and enhanced data rate traffic. The low-IF receiver is also optimized, requiring very little analog filtering and using an oversampled analog- to-digital converter to move the filtering burden to the digital domain. The result is the smallest and lowest power Bluetooth radio published to date.