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A test chip has been built to study the effects of circuit layout on variability, and to characterize within-die (WID) and die-to-die (D2D) variability of delay and leakage current in 90 nm CMOS technology. Delay is obtained through the measurement of ring oscillator frequencies, and the transistor leakage current is measured by an on-chip analog-to-digital converter (ADC). It has been found that the transistor performance depends strongly on the polysilicon (poly-Si) gate density, and the spatial correlation depends on the gate orientation and the direction of poly-Si spacing. WID variation is small with three standard deviations over a mean (3sigma/mu) of around 3.5%, whereas D2D and systematic layout-induced variations are significant, with a 3sigma/mu D2D variation of ~15% and a maximum layout-induced frequency shift of 10%. Finally, a set of guidelines is proposed to help circuit designers mitigate the effects of process variations on CMOS performance.