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A 1 GHz Bandwidth Low-Pass \Delta \Sigma ADC With 20–50 GHz Adjustable Sampling Rate

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2 Author(s)
Hart, A. ; Edward S. Rogers, Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON ; Voinigescu, S.P.

A low-pass continuous-time delta-sigma data converter with adjustable sampling rate from 20-50 GS/s has been demonstrated in a production 165 GHz-fT 130-nm SiGe BiCMOS process. The ADC exploits the high transistor fT of modern silicon technologies to achieve an ENOB of 7 bits over a 500 MHz passband and 6 bits over a 1 GHz passband while consuming 350 mW from a 2.5 V supply (650 mW including on chip clock distribution and output driver); marking the first delta-sigma ADC to reach a bandwidth of 1 GHz. At the system-level, the analysis of a detailed behavioral model brought to light the high dependency of modulator performance on metastability. An analytical expression linking quantizer gain and number of bits to performance was therefore derived and used to estimate the theoretical limitations imposed by metastability.

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Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 5 )