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Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

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4 Author(s)
Matteo Agostinelli ; Inst. of Networked & Embedded Syst., Univ. of Klagenfurt, Klagenfurt, Austria ; Massimo Alioto ; David Esseni ; Luca Selmi

In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bulk MOSFETs when low standby power circuit techniques are implemented. More precisely, we simulated various vehicle circuits, ranging from ring oscillators to mirror full adders, to investigate the effectiveness of back biasing and transistor-stacking in both FinFETs and bulk MOSFETs. The opportunity to separate the gates of FinFETs and to operate them independently has been systematically analyzed; mixed connected- and independent-gate circuits have also been evaluated. The study spans over the device, the layout, and the circuit level of abstraction and appropriate figures of merit are introduced to quantify the potential advantage of different schemes. Our results show that, thanks to a larger threshold voltage sensitivity to back biasing, the FinFET technology is able to offer a more favorable compromise between standby power consumption and dynamic performance and is well suited for implementing fast and energy-efficient adaptive back-biasing strategies.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:18 ,  Issue: 2 )