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Shared-memory architecture to implement a high-connectivity processing node

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4 Author(s)
F. Ancona ; Genoa Univ., Italy ; D. Anguita ; S. Rovetta ; R. Zunino

The Letter describes the implementation of a high-connectivity processing node by means of an embedded shared dual-port memory. The memory is accessed directly by two transputers in order to realise a virtual processor with a connectivity and a computing power that are twice those of a single transputer

Published in:

Electronics Letters  (Volume:31 ,  Issue: 22 )