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Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing

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7 Author(s)
Kapetanakis, E. ; Institute of Microelectronics, NCSR Demokritos, 15310 Aghia Paraskevi, Greece ; Normand, P. ; Tsoukalas, D. ; Beltsios, K.
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Thin SiO2 oxides implanted by very-low-energy (1 keV) Si ions and subsequently annealed are explored with regards to their potential as active elements of memory devices. Charge storage effects as a function of Si fluence are investigated through capacitance and channel current measurements. Capacitance–voltage and source–drain current versus gate voltage characteristics of devices implanted with a dose of 1×1016cm-2 or lower exhibit clear hysteresis characteristics at low electric field. The observed fluence dependence of the device electrical properties is interpreted in terms of the implanted oxide structure. © 2000 American Institute of Physics.

Published in:

Applied Physics Letters  (Volume:77 ,  Issue: 21 )

Date of Publication:

Nov 2000

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