Referenced Items are not available for this document.
Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.122401
A compact single-electron memory cell has been fabricated in silicon using a process that is compatible with complementary metal–oxide–semiconductor circuit fabrication. The device is based on the Coulomb blockade effect observed in highly doped silicon nanowires. The circuit shows clear memory operation with a ≫100 mV gap between “0” and “1” levels when tested at a temperature of 4.2 K. The response of the circuit to write and erase pulse sequences is also presented. © 1998 American Institute of Physics.
Published in:
Applied Physics Letters
(Volume:73
,
Issue:
15
)
Date of Publication: Oct 1998
- Page(s):
- 2134 - 2136
- ISSN :
- 0003-6951
- Digital Object Identifier :
- 10.1063/1.122401
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 18 June 2009
- Issue Date :
- Oct 1998
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
