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The pad structure of CMOS technology is characterized by way of time domain reflectometry measurement. Using the on-wafer TDR measurement system, the capacitance of the pad in the CMOS process was extracted and estimated. Measured and simulated TDR data are also presented in this study. The capacitance is estimated when the curve is fitted by mathematical tool. This method is simple to use, and furthermore the results agree with data extracted from vector network analyzer.