By Topic

Self timed division and square-root extraction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Guyot, A. ; Integrated Syst. Design Group, TIMA-UJF, Grenoble, France ; Renaudin, M. ; El Hassan, B. ; Levering, V.

This paper describes a self-timed integrated circuit for division and square-root extraction. First it concentrates on the development and the proof of a new mathematical algorithm. Then the design methodology and the architecture of a self-timed circuit implementing a simplified version of the algorithm is presented. The algorithm relies on two functional blocks, each simple enough to be fully detailed at the logic level in this paper. Besides its simplicity, the novelty of the algorithm lies in the fact that it delivers the quotient or the square root in conventional binary notation. The final remainder only has to be eventually converted

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996