Self timed division and square-root extraction

This paper describes a self-timed integrated circuit for division and square-root extraction. First it concentrates on the development and the proof of a new mathematical algorithm. Then the design methodology and the architecture of a self-timed circuit implementing a simplified version of the algorithm is presented. The algorithm relies on two functional blocks, each simple enough to be fully detailed at the logic level in this paper. Besides its simplicity, the novelty of the algorithm lies in the fact that it delivers the quotient or the square root in conventional binary notation. The final remainder only has to be eventually converted.