By Topic

Low power realization of FIR filters using multirate architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Mehendale, M. ; Texas Instrum. (India) Ltd., Bangalore, India ; Sherlekar, S.D. ; Venkatesh, G.

The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996