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Ultra low power digital signal processing

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1 Author(s)
Chandrakasan, A.P. ; MIT, Cambridge, MA, USA

The explosive growth of portable wireless devices has elevated power consumption to be one of the most critical design parameters. This paper presents several techniques to implement DSP functions with the lowest possible power consumption. Since power is consumed only when capacitance is being switched, power can be reduced by minimizing this capacitance through operation reduction, choice of data representation, exploitation of spatial and temporal signal correlations, re-synchronization to minimize glitching, and logic, circuit and physical design. Aggressive voltage scaling to 1 V and below through circuit and architecture optimization is the key to low-power design. A systems approach to low-power design can result in orders of magnitude power reduction

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996