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Statistical path delay fault coverage estimation for synchronous sequential circuits

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4 Author(s)
Pappu, L. ; CAIP Center, Rutgers Univ., Piscataway, NJ, USA ; Bushnell, M.L. ; Agrawal, V.D. ; Srinivas, M.K.

We present the first technique to statistically estimate path delay-fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multi-valued algebra and accumulate signal statistics, which we use to calculate path delay-fault coverage. The detectability of a path delay-fault is the product of observabilities from primary or pseudo-primary outputs to primary or pseudo-primary inputs, and the controllability on the corresponding primary or pseudo-primary inputs. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with fault simulation results, the average error in statistical fault coverage using our technique is 2%. On average, the method accelerates fault coverage calculation two to five times over a delay-fault simulator, when all paths are considered

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996