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Comprehensive electrothermal analysis of multilevel interconnects under electrostatic discharge (ESD) stress is carried out using the proposed nonlinear time-domain finite-element method (FEM). The technological, structural, and material parameters used in the analysis correspond to the advanced CMOS process of 90-, 65-, 45, and 32-nm nodes assessed by the International Technology Roadmap for Semiconductors. In order to enhance the computation efficiency and to reduce the memory cost, the preconditioned conjugated gradient technique combined with the element-by-element approximate factorization method is introduced to handle the sparse matrices formed by FEM. The nonlinear material parameters including the temperature-dependent electrical and thermal conductivities are treated rigorously. The transient temperature distributions, the maximum temperatures, and the temperature rise time of 3- and 4-level interconnect structures under the injection of ESD pulses with various waveforms are obtained and discussed.