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Integration of High- \kappa Dielectrics and Metal Gate on Gate-All-Around Si-Nanowire-Based Architecture for High-Speed Nonvolatile Charge-Trapping Memory

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5 Author(s)
Fu, J. ; Inst. of Microelectron., Agency for Sci., Technol. & Res. (A* STAR), Singapore ; Singh, N. ; Zhu, Chunxiang ; Guo-Qiang Lo
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This letter, for the first time, presents a metal high-kappa -high-kappa-oxide silicon-type charge-trapping nonvolatile memory fabricated on an advanced gate-all-around nanowire architecture with a top-down process. The high-kappa materials are integrated with a high work-function TaN gate electrode. The fabricated Si nanowire TaN/ Al2O3/HfO2/SiO2/Si (TAHOS) memory can achieve a higher speed at a lower voltage compared with a similar wire-based SONOS device. For instance, at a 13-V programming pulse, the TAHOS memory device resulted in a V th shift of 3.8 V in 10 mus, while the SONOS took a period of 1 ms to produce a similar shift. Faster program-and-erase speed, particularly the much improved erasing speed in the TAHOS device, could be ascribed to the enhanced electric-field drop in the tunnel oxide in addition to the suppressed gate-electron injection. In addition, good memory-reliability properties could also be observed in the nanowire TAHOS charge-trapping memory.

Published in:

Electron Device Letters, IEEE  (Volume:30 ,  Issue: 6 )