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Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

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4 Author(s)
Horng-Chih Lin ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu ; Wei-Chen Chen ; Chuan-Ding Lin ; Tiao-Yuan Huang

A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.

Published in:

IEEE Electron Device Letters  (Volume:30 ,  Issue: 6 )