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“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

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4 Author(s)
McNeill, J.A. ; Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA ; David, C. ; Coln, M. ; Croughwell, R.

The ldquosplit analog-to-digital converter (ADC)rdquo architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of M interleaved ADCs requires 2M + 1 half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:56 ,  Issue: 5 )