Close category search window
 

On more efficient combinational ATPG using functional learning

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Mukherjee, R. ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; Jain, J. ; Fujita, M. ; Abraham, J.A.
more authors

Learning techniques like SOCRATES and recursive learning have greatly enhanced the technology of FAN-based ATPG. In this paper we present a test generation methodology for combinational circuits using functional learning, discuss application of novel functional information to enhance ATPG and present ATPG results on ISCAS 85 benchmark circuits. The test generation methodology combines the use of structural (topology) based analysis methods with the function representation techniques (such as BDDs)

Published in:
VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference: 3-6 Jan 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.