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Instruction-set matching and GA-based selection for embedded-processor code generation

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3 Author(s)
J. Shu ; Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada ; T. C. Wilson ; D. K. Banerji

The core tasks of retargetable code generation are instruction-set matching and selection for a given application program and a DSP/ASIP processor. In this paper, we utilize a model of target architecture specification that employs both behavioral and structural information, to facilitate this process. The matching method is based on a pattern tree structure of instructions. This tree structure, generated automatically, is implemented by using a pattern queue and a flag table. The matching process is efficient since it bypasses many patterns in the tree which do not match at certain nodes in the DFG of given application program. Two genetic algorithms are implemented for pattern selection: a pure GA which uses standard GA operators, and a GA with backtracking which employs variable-length chromesomes. Optimal or near-optimal pattern selection is obtained in a reasonable period of time for a wide range of application programs

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996