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A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications

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2 Author(s)
Poornaiah, D.V. ; Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India ; Ananda Mohan, P.V.

In this paper, an efficient algorithm for concurrent computation of two real multiplications and/or two real additions usually required for high-throughput image and video coding applications is described. The proposed algorithm is mapped onto a novel concurrent dual multiplier-dual adder cell based on carry-save 4:2 compressors. A detailed performance analysis of the the proposed cell shows reductions ranging from 15% to 60% in the computation time and area when compared with the conventional processing elements making it highly attractive for VLSI implementation

Published in:

VLSI Design, 1996. Proceedings., Ninth International Conference on

Date of Conference:

3-6 Jan 1996