By Topic

Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expression

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Titus, J.L. ; Naval Surface Warfare Center, Crane, IN, USA ; Wheatley, C.F. ; Burton, D.I. ; Mouret, I.
more authors

This paper investigates the role that the gate oxide thickness (T ox) plays on the gate and drain failure threshold voltages required to induce the onset of single-event gate rupture (SEGR). The impact of gate oxide thickness on SEGR is experimentally determined from vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) having identical process and design parameters, except for the gate oxide thickness. Power MOSFETs from five variants were specially fabricated with nominal gate oxide thicknesses of 30, 50, 70, 100, and 150 nm. Devices from each variant were characterized to mono-energetic ion beams of Nickel, Bromine, Iodine, and Gold. Employing different bias conditions, failure thresholds for the onset of SEGR were determined for each oxide thickness. Applying these experimental test results, a previously published empirical expression is extended to include the effects of gate oxide thickness. In addition, observations of ion angle, temperature, cell geometry, channel conductivity, and curvature at high drain voltages are briefly discussed

Published in:

Nuclear Science, IEEE Transactions on  (Volume:42 ,  Issue: 6 )