By Topic

A comparison of fault-tolerant state machine architectures for space-borne electronics

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. Niranjan ; Cirrus Logic, Fremont, CA, USA ; J. F. Frenzel

Very large scale integrated (VLSI) circuits used in the space and nuclear industry are continuously subjected to ion radiation. As the limits of VLSI technology are pushed towards sub-micron levels in order to achieve higher levels of integration, devices become more vulnerable to radiation induced errors. These radiation induced errors can lead to system failure, particularly if they affect the memory portion of vital subsystems, such as state machine controllers. This paper explores the use of classical fault-tolerant state machine architectures based on hardware and information redundancy to design radiation-immune controllers. Those architectures particularly suitable for VLSI-implementation using ordinary low power CMOS technology are identified, with the primary objective of correcting single flip-flop errors. Each architecture was implemented on a set of benchmark sequential circuits and evaluated in terms of circuit-size and maximum path-delay. The best overall architectures, `SEU-I TMR' and `Modified Explicit EC', used a nonredundant excitation circuit and redundant flip-flops, followed by error correction circuitry to tolerate single flip-flop errors

Published in:

IEEE Transactions on Reliability  (Volume:45 ,  Issue: 1 )