Referenced Items are not available for this document.
The use of a low temperature grown GaAs (LT GaAs) buffer layer in GaAs FETs is shown via computer simulation and experimental measurement to reduce ion-induced charge collection by two to three orders of magnitude. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the FETs. Error rate calculations indicate that the soft error rate of LT GaAs integrated circuits will be reduced by several orders of magnitude when compared to conventional FET-based GaAs ICs
Published in:
Nuclear Science, IEEE Transactions on
(Volume:42
,
Issue:
6
)
Date of Publication: Dec 1995
- Page(s):
- 1837 - 1843
- ISSN :
- 0018-9499
- INSPEC Accession Number:
- 5179748
- Digital Object Identifier :
- 10.1109/23.488787
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec 1995
- Sponsored by :
- IEEE Nuclear and Plasma Sciences Society
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