By Topic

A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

19 Author(s)
Nitta, Y. ; Adv. Technol. R&D., Mitsubishi Electr. Corp., Itami, Japan ; Sakashita, N. ; Shimomura, K. ; Okuda, F.
more authors

This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.

Published in:

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Date of Conference:

10-10 Feb. 1996