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Design of high-speed and cost-effective self-testing checkers for low-cost arithmetic codes

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1 Author(s)
Piestrak, S.J. ; Inst. of Power Syst. Autom., Wroclaw, Poland

Methods for designing self-testing checkers (STCs) for arithmetic error-detecting codes are presented. First, general rules for the design of minimal-level STCs for any error-detecting code are given. The design is illustrated with STCs for 3N+B codes, 0⩽B ⩽2. Then the recursive structure of both 3N+B codes and residue/inverse-residue codes with check base A=3 is revealed. The resulting design of STCs is very flexible and universal, in the sense that an iterative, cost-effective, or high-speed version of the checker can be designed for either code. The design approach, unlike previous approaches for arithmetic codes, gives a unified treatment to STCs for nonseparate (3N+B) and separate (residue and inverse residue) codes. The speed and the complexity of the STC for a code from either class with n bits are about the same. Both high-speed checkers (which have up to three gate levels) and cost-effective checkers are faster and require less hardware than analogous checkers proposed for 3N codes and for residue codes with A=3

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Computers, IEEE Transactions on  (Volume:39 ,  Issue: 3 )