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Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers

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1 Author(s)
G. S. Sohi ; Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA

The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts is presented. Simulation studies show that by resolving dependencies the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts

Published in:

IEEE Transactions on Computers  (Volume:39 ,  Issue: 3 )