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A 200M sample/s 6b flash ADC in 0.6 /spl mu/m CMOS

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2 Author(s)
Spalding, J. ; Raheen Ind. Estate, Analog Devices Inc., Limerick, Ireland ; Dalton, D.

This 6b flash analog-to-digital converter (ADC) performs the sampling function in a partial-response, maximum-likelihood disk drive read channel. The read channel must process signals with spectral content extending up to half the sampling rate. This requires an ADC with better than 5 effective bits at Nyquist, accomplished here using a full-flash architecture capable of sampling at 200 MHz. To meet cost objectives, the read channel is on 0.6 /spl mu/m single-poly CMOS, where the ADC achieves performance previously seen only on bipolar or BiCMOS processes.

Published in:

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Date of Conference:

10-10 Feb. 1996