Referenced Items are not available for this document.
This cache operates at 10 mW, and 100 MHz at 1 V supply using separated bit-line memory hierarchy architecture (SBMHA) that reduces latency and power, and domino tag comparators (DTCs) that reduce dissipation of tag comparisons. On-chip caches in low-power microprocessors need high bit-ratio to reduce power. Higher bit-ratio is achieved using a larger cache. But this has the drawback of longer latency. The SBMHA hides the long latency.
Published in:
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Date of Conference: 10-10 Feb. 1996
- Page(s):
- 152 - 153
- Meeting Date :
- 08 Feb 1996-10 Feb 1996
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-3136-2
- INSPEC Accession Number:
- 5310186
- Conference Location :
- San Francisco, CA, USA
- Digital Object Identifier :
- 10.1109/ISSCC.1996.488549
- Product Type:
- Conference Publications
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