Skip to Main Content
An embedded 5 V only 16 M flash memory has an on-chip state machine that generates embedded program and erase algorithms, eliminating system execution of these operations. The system issues a series of commands decoded by the state machine for on-chip execution. It is a /spl times/8 part with a read/busy pin to indicate to the system if the part is in an embedded mode, and a RESETB pin to terminate any operation being executed by the state machine and reset the part to the read mode. Erase is by applying a negative voltage to the control gate of the array and a positive voltage VS to the sector array source.