Skip to Main Content
A 64 Mb flash memory has a multi-level cell and 64-memory-cell parallel programming. 98 mm/sup 2/ die uses 0.4 /spl mu/m CMOS and 4-levels (2b) per cell. 3.3 V operation and 6.3 /spl mu/s/B programming are achieved by using a Fowler-Nordheim (FN) NOR memory cell. Drain-voltage controlled multilevel programming (DCMP) is the key technology for simultaneous multi-level programming in the chip. To implement DCMP, a parallel multi-level verify (PMV) circuit and the compact multi-level sense amplifier (CMS), which enable a 64-memory-cells parallel programming operation (program/program verify), are used.