By Topic

Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
K. M. Sharaf ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; M. I. Elmasry

An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented. The analytical delay model accounts for all the device parasitics and the device sizes of the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay). A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model

Published in:

IEEE Journal of Solid-State Circuits  (Volume:31 ,  Issue: 2 )