By Topic

Nonstuck behaviour of open circuit supply faults in CMOS logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. Johnson ; Sch. of Eng., Durham Univ., UK ; M. J. Morant

The authors describe a mechanism which allows CMOS circuits containing a break in a power supply track (referred to as open circuit supply faults) to operate with little change in their performance parameters. In circuits containing such faults, current can be supplied through the substrate or well contacts enabling logic gates to operate at full design speed. Measurements on circuits containing such faults and results of simulations are presented to demonstrate the effect of the fault. The circuits operate normally, although they may be susceptible to latch-up behaviour and may fail in this way. Transient latch-up testing is recommended to detect such faults

Published in:

IEE Proceedings - Circuits, Devices and Systems  (Volume:143 ,  Issue: 1 )