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Multiple-inputs systolic priority queue for fast sequential decoding of convolutional codes

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2 Author(s)
Kuo, H.-C. ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Wei, C.-H.

The operating speed of a sequential decoder with stack algorithm is usually limited by the time to search the best node for further extension. This problem can be completely alleviated by using the systolic priority queue to replace the stack memory. However, the systolic priority queues developed previously are accessible only in the cases when the number of inputs processed is small. This is because the complexity of a queue grows up quickly as the volume of data flowing through it increases. Since the largest amount of data flowing through a systolic priority queue is equal to the number of inputs to this queue, the systolic priority queue is not suitable for a system with many inputs. A modified version of previously developed circuits is proposed. The number of transmission gates required in this circuit is proportional to 3N instead of N2, where N is the number of inputs. Also the total number of control signals is proportional to 3N 2 instead of N3. But the number of comparators required is proportional to C2N+1, as before. This modified circuit can be used in cases where the number of inputs is small (N⩽8). A new algorithm for the multiple-inputs systolic priority queue (MISPQ) is proposed. By using this algorithm, a MISPQ may be implemented with several smaller queues, each is used to process a part of data in the MISPQ. Since the volume of data flowing through each queue is small, these queues will be simpler. However, some additional circuits should be used for the interactions between queues. A circuit for implementing this algorithm is presented and its complexity is analysed. The number of transmission gates for the MISPQ is proportional to 3N, the number of control signals is proportional to (3N2/2), and the number of comparators is proportional to 4C 2N/2+1. Thus this new architecture is feasible for large N (e.g.N⩾8)

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:142 ,  Issue: 5 )

Date of Publication:

Oct 1995

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