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Non-referenced prefetch (NRP) cache for instruction prefetching

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4 Author(s)
Park, G.H. ; Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea ; Kwon, O.-Y. ; Han, T.D. ; Kim, S.-D.

A new conceptual cache, NRP (nonreferenced prefetch) cache, is proposed to improve the performance of instruction prefetch mechanisms which try to prefetch both the sequential and nonsequential blocks under limited memory bandwidth. The NRP cache is used for storing prefetched blocks that were not referenced by the CPU. These blocks were discarded in previous prefetch mechanisms. By storing the non-referenced prefetch blocks in the NRP cache, both cache misses and memory traffic are reduced. A prefetch method to prefetch both the sequential and the nonsequential instruction paths is designed to utilise the effectiveness of the NRP cache. The results from trace-driven simulation show that this approach provides an improvement in memory access time compared to other prefetch methods. Particularly, the NRP cache is more effective in a lookahead prefetch mechanism that can hide longer memory latency. Also, the NRP cache reduces the additional memory traffic required to prefetch both instruction paths. This approach can achieve both improved memory access time and reduced memory traffic in a cost-effective cache design

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:143 ,  Issue: 1 )

Date of Publication:

Jan 1996

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