By Topic

Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Masahara, M. ; Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan ; Yongxun Liu ; Ishii, Kenichi ; Sakamoto, Kunihiro
more authors

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.1891289 

For gate work function engineering required for ultrathin channel (UTC) double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET), threshold voltage (Vth) tuning of self-aligned asymmetric (n+–p+) DG MOSFETs have been experimentally investigated in comparison with symmetric (n+–n+) DG MOSFETs. The vertical UTCs (12–32 nm) were fabricated on bulk Si substrates by utilizing the novel ion-bombardment-retarded wet etching and the self-aligned asymmetric DGs were formed by employing the tilted ion implantation and anisotropic dry etching. The fabricated vertical asymmetric DG n-MOSFET with the gate length of 100 nm clearly exhibits the desirable Vth of +0.1 V, in addition to the unique DG MOSFET characteristics of the high short-channel-effect immunity with decreasing a channel thickness.

Published in:

Applied Physics Letters  (Volume:86 ,  Issue: 12 )