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Reliability assessment of EPROM memory retention for wafer level sort programming

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2 Author(s)
Teong-San Yeoh ; Intel Technol., Penang, Malaysia ; Shze-Jer Hu

The feasibility of programming microcontroller EPROM memory in the wafer sort operation instead of the backend test operation is studied. The major concern is EPROM charge loss due to heat treatments during the assembly processing. Theoretical and experimental evaluations as discussed in this paper have shown that wafer level sort programming is a viable option with no impact to quality and reliability

Published in:

Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the

Date of Conference:

27 Nov-1 Dec 1995