Voltage-induced degradation in self-aligned polycrystalline silicon gate n-type field-effect transistors with HfO₂ gate dielectrics

The voltage-induced degradation in the threshold voltage of field-effect transistors using atomic layer deposited HfO₂-gate dielectrics was studied. Si channel surfaces of some samples were in situ pretreated using O₃ flow before HfO₂ deposition, which formed a very thin SiO₂ interfacial layer. This avoided a shift of the threshold voltage up to a stress time of 1000 s under inversion condition at +3 V gate voltage. The transistors without O₃ pretreatment showed a serious change in the threshold voltage by electron trapping. A leakage current measurement under inversion condition showed that the leakage current was not the major factor that controlled the degradation. Instead, the interfacial traps resulting from the Si suboxide formation for the cases without O₃ pretreatment appeared to constitute the major reason for the degradation.