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The scalable processor architecture (SPARC)

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12 Author(s)
Garner, R.B. ; Sun Microsyst. Inc., Mountain View, CA, USA ; Agrawal, A. ; Briggs, F. ; Brown, E.W.
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An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor. A brief comparison with Berkeley RISC (reduced-instruction-set-computer) and SOAR is provided.<>

Published in:

Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers

Date of Conference:

Feb. 29 1998-March 3 1988