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Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

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2 Author(s)
Zhang, Wei ; NanoStructure Laboratory, Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 ; Chou, S.Y.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.1600505 

Nanoimprint lithography (NIL) is a paradigm-shift method that has shown sub-10-nm resolution, high throughput, and low cost. To make NIL a next-generation lithography tool to replace conventional lithography, one must demonstrate the needed overlay accuracy in multilayer NIL, large-area uniformity, and low defect density. Here, we present the fabrication of 60-nm channel metal–oxide–semiconductor field-effect transistors on whole 4-in. wafers using NIL at all lithography levels. The nanotransistors exhibit excellent operational characteristics across the wafer. The statistics from consecutive multiwafer processing show an average overlay accuracy of 500 nm over the entire 4-in. wafer. The accuracy is much better when the field size is reduced. The overlay accuracies are limited by the current alignment method and can be improved substantially. The work presents a significant advance in nanoimprint development and its applications in manufacturing of integrated electrical, optical, chemical, and biological nanocircuits. © 2003 American Institute of Physics.

Published in:
Applied Physics Letters  (Volume:83 ,  Issue: 8 )

Date of Publication: Aug 2003

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