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Effective dielectric constants of advanced interconnects with low-k and ultra-low-k dielectrics were evaluated by two-dimensional capacitance analysis. The analysis was performed for interconnect design rules proposed for 65 nm node high-performance integration. Interconnects with various pitches and integration schemes were examined, and the effects of supporting dielectric layers including cap layer, chemical mechanical polishing stop layer, and etch stop layer were evaluated. The results indicated that the use of the supporting layers greatly affects the effective dielectric constant of interconnect structures. The impacts of the supporting dielectric layers on the effective dielectric constant were evaluated quantitatively, and the implications on back-end-of-line integration schemes were discussed. © 2003 American Institute of Physics.