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Correlation between interface traps and gate oxide leakage current in the direct tunneling regime

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3 Author(s)
Wei Yip Loh ; Silicon Nano Device Laboratory (SNDL), Department of Electrical and Computer Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260 ; Jin Cho, Byung ; Li, Ming Fu

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Our experiment shows that when the gate oxide thickness is scaled to direct tunneling regime, the gate leakage current, and the number of interface traps increase in a discrete manner rather than in a gradual increment. A direct correlation between the increments of the gate leakage current and interface traps, irrespective of stressing polarity, is also observed. The discrete increase in gate current is due to degradation at localized spots rather than a uniform degradation over the entire gate area. The increment is also observed over a wide voltage range unlike interface-trap-assisted tunneling previously reported which occurs mainly near the flat-band voltage. A possible mechanism is proposed based on the observations. © 2002 American Institute of Physics.

Published in:

Applied Physics Letters  (Volume:81 ,  Issue: 2 )