Fabrication of Si single-electron transistors having double SiO₂ barriers

We fabricated Si single-electron transistors (SETs) having double SiO₂ barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (I_d) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the I_d oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use. © 2002 American Institute of Physics.