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Improving SiO2/SiGe interface of SiGe p-metal–oxide–silicon field-effect transistors using water vapor annealing

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4 Author(s)
Ngai, T. ; Microelectronics Research Center, The University of Texas, 10100 Burnet Road, Austin, Texas 78758 ; Chen, X. ; Chen, J. ; Banerjee, S.K.

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SiGe p-metal–oxide–silicon field-effect transistors (p-MOSFETs) were fabricated with ultrathin thin (∼20 Å) remote plasma chemical vapor deposition gate oxides deposited directly on SiGe. A low temperature water vapor annealing was used to improve the SiO2/SiGe interface and performance of SiGe p-MOSFETs. After the wet annealing, dangling Si and Ge bonds at the interface are passivated by atomic hydrogen, the threshold voltage of SiGe p-MOSFETs decreases from -0.39 to -0.20 V, the subthreshold slope from 117 to 87 mV/dec, and more than 20% output current enhancement is observed in these SiGe p-MOSFETs compared with Si control devices. © 2002 American Institute of Physics.

Published in:

Applied Physics Letters  (Volume:80 ,  Issue: 10 )