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Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays

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4 Author(s)
Belabbes, N.-E. ; Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada ; Guterman, A.J. ; Savaria, Y. ; Dagenais, M.

Fault detection and fault-tolerance in modular processing arrays are reviving the use of majority voting techniques. In this paper, a simple voting circuit structure, called a ratioed voter, is analyzed to prove its reliable operation when Dynamic N-Modular Redundant (DNMR) tuples are configured for testing in fault-tolerant processing arrays. Its application in VLSI design for self-testing would lead to low area overhead and high diagnosability, both contributing to improve yield. Moreover, the flexibility of such a structure, which allows modulation of the voting level (N), permits a common approach for fabrication-time and on-line testing

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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:43 ,  Issue: 2 )