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VLSI architectures for block matching algorithms using systolic arrays

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3 Author(s)
Sung Bum Pan ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; Seung Soo Chae ; Rae-Hong Park

We investigate hardware implementation of block matching algorithms (BMAs) for motion estimation of moving sequences. Using systolic arrays, we propose VLSI architectures for the two-stage BMA and full search (FS) BMA. The two-stage BMA using integral projections reduces greatly the computational complexity with its performance comparable to that of the FS BMA. The proposed hardware architectures for the two-stage BMA and FS BMA are faster than the conventional hardware architectures with lower hardware complexity. Also, the proposed architecture of the first stage of the two-stage BMA is modeled in VHDL and simulated. Simulation results show the functional validity of the proposed architecture

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IEEE Transactions on Circuits and Systems for Video Technology  (Volume:6 ,  Issue: 1 )