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A discrete syntax for level-sensitive latched circuits having n clocks and m phases

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2 Author(s)
G. Jennings ; Div. of Comput. Eng., Lulea Univ. of Technol., Sweden ; E. Jennings

We present a syntax which allows the discrete specification of semantically unambiguous level-sensitive latched circuits for an unprecedented class of complex and unrestricted sequencing schemes. Circuits obeying the syntax are timing-robust, even though the syntax contains no linear timing, delay or skew specifications. The syntax provides a constructive definition of a correct circuit by formulating the circuit according to a discrete clocking subsyntax and a delay-independent circuit subsyntax, which together need only comply with two rules. The syntax defines a class of latched circuits which are provably oscillation-free, race-free, always able to comply with setup and hold time constraints, and are always implementable given the freedom to slow the clocks down sufficiently. The formalism can cope with edge-triggered synchronizers, and with qualified clocking as found in gated latching. Compliance check times for the syntax are linear in the size of the circuit. As motivation for the formalism we give an example of a timing synthesis derived directly from the syntax, for a polyrhythmically clocked chip ensemble

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:15 ,  Issue: 1 )