By Topic

A novel framework for logic verification in a synthesis environment

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kunz, W. ; Group for Fault-Tolerant Comput., Univ. of Potsdam, Germany ; Pradhan, D.K. ; Reddy, S.M.

A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural (logic network) approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural (logic network) information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 1 )