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Built-in self-test (BIST) design of high-speed carry-free dividers

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1 Author(s)
Chin-Long Wey ; Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:4 ,  Issue: 1 )