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System design for pixel-parallel image processing

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4 Author(s)
Gealow, J.C. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Herrmann, F.P. ; Hsu, L.T. ; Sodini, C.G.

A system design for performing low-level image processing tasks in real time is presented. The design is based on large processor-per-pixel arrays implemented using integrated circuit technology. Two integrated circuit architectures are summarized: an associative parallel processor and a parallel processor employing DRAM cells. In both architectures, the layout pitch of one-bit-wide logic is matched to the pitch of memory cells to form high-density processing element arrays. The system design features an efficient control path implementation, providing high processing element array utilization without demanding complex controller hardware. Sequences of array instructions are generated by a host computer before processing begins, then stored in a simple controller. Once processing begins, the host computer initiates stored sequences to perform pixel-parallel operations. A programming framework implemented using the C++ programming language supports application development. A prototype system employs associative parallel processor devices, a controller, and the programming framework. Three sample applications, smoothing and segmentation, median filtering, and optical flow, establish the suitability of the system for real-time image processing.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:4 ,  Issue: 1 )