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Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC

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2 Author(s)
Zhihao Lao ; Mikroelektronik Zentrum, Ruhr-Univ., Bochum, Germany ; Langmann, Ulrich

The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 1 )